ASAHI KASEI

[AKD4382]

'00/09

- 1 -

GENERAL DESCRIPTION

The AKD4382 is an evaluation board for the AK4382, the 24bit, 192kHz D/A converter for DVD and AC-
3 amp. The AKD4382 has the interface with AKM's wave generator using ROM data and with AKM's A/D
converter evaluation boards. Therefore, it is easy to evaluate the AK4382. The AKD4382 also has the
digital audio interface and can achieve the interface with digital audio systems via opt-connector or BNC
connector.

Ordering guide

AKD4382

---

Evaluation board for AK4382

(Cable for connecting with printer port of IBM-AT compatible PC
and control software are packed with this.)

FUNCTION

�

On-board 2nd order LPF

�

Compatible with 2 types of interface

- Direct interface with AKM's A/D converter evaluation boards
and direct interface with AKM's signal generator(AKD43XX) by 10pin header
- On-board AK4112A as DIR which accepts optical or BNC input

�

10pin header for serial control interface

-15V

GND

AK4112A

(DIR)

Opt In

10pin Header

A/D Data
ROM Data

AK4382

Rch

COAX In

Lch

Output

LPF

10pin Header

Control Data

+15V

Regulator

Figure 1. AKD4382 Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

Evaluation board Rev.A for AK4382

AKD4382

ASAHI KASEI

[AKD4382]

'00/09

- 2 -

External analog circuit

The 2nd order LPF (fc=93.2kHz, Q=0.712) which adds differential outputs of the AK4382 is implemented on the board.
When the further attenuation of the out-band noise is needed, some additional LPF is required. Analog signal is output
through BNC connectors on the board. And the output level of the AK4382 is 5.5Vpp@5V.

LOUT-
(ROUT-)

LOUT+
(ROUT+)

+15V

-15V

NJM5532D

22u

10k

220

Figure 2. On-board analog filter

4.7k

200

3300p

470p

Table 1. The value of R,C on this board

fin

20kHz

40kHz

80kHz

Frequency Response

-0.003dB

-0.122dB

-1.821dB

Table 2. Frequency Response of LPF

fc=

Amplitude = 20 log

[1-(f/fc)

]

+[(1/Q)(f/fc)]

[dB],

ASAHI KASEI

[AKD4382]

'00/09

- 3 -

Operation sequence

1) Set up the power supply lines.

[+15V]

(orange)

= +12

+15V

[-15V]

(blue)

= -12

-15V

[4382_VDD] (red)

= 4.75

5.25V (Note 2)

[AGND]

(black)

= 0V

[DGND]

(black)

= 0V

Note:

1. Each supply line should be distributed from the power supply unit.

2. JP3(REG) should be shorted and "4382_VDD" jack should be open if VDD of the AK4382 is supplied

from the regulator.

2) Set-up the evaluation modes, jumper pins and DIP switches

(See the followings.)

3) Power on.

The AK4382 should be reset once bringing SW1(PDN) "L" upon power-up.

Evaluation mode

Applicable evaluation modes

1) DIR (Optical Link or BNC) (default)
2) Using ROM data (AK43XX)
3) Using AKM's evaluation board for ADC
4) Feeding all signals from external

1) DIR (Optical Link or BNC) <default>

The AK4112A(DIR) generates MCLK, BICK, LRCK and SDATA from the received data through
PORT1(TORX176: optical link) or J1(BNC). Used for the evaluation using CD test disk. Nothing should be
connected to PORT2(EXT). In case of using optical connector (TORX176), JP1(TORX/BNC) should be selected
to "TORX". In case of using BNC connector, select "BNC".

JP4

MCLK

JP5

BICK

JP6

SDATA

JP7

LRCK

2) Ideal sine wave generated by ROM data

Connect the AKD43XX with PORT2(EXT). The AKD4382 sends MCLK to the AKD43XX which the
AK4112A(DIR) generates from the received data through PORT1(TORX176: optical link) or J1(BNC). And the
AKD4382 receives LRCK, BICK and SDATA from the AKD43XX.

JP4

MCLK

JP5

BICK

JP6

SDATA

JP7

LRCK

ASAHI KASEI

[AKD4382]

'00/09

- 4 -

3) Using AKM's evaluation board for ADC

To evaluate the AK4382 with analog input, the AKM's evaluation board for ADC can be used. MCLK, BICK and
LRCK and A/D converted data are sent to the AKD4382 through PORT2(EXT) via 10 pin flat cable.

JP4

MCLK

JP5

BICK

JP6

SDATA

JP7

LRCK

4) Feeding all signals from external

Under the following set-up, all external signals can be fed through POTR2(EXT).

JP4

MCLK

JP5

BICK

JP6

SDATA

JP7

LRCK

DIP switch(S1) set up

S1 sets the mode of the AK4112A. Set-up is needed only for the evaluation mode 1 and 2. ON is "H" and OFF is

"L".

No.

Default

Introduction

CM0

OFF

CM1

OFF

Clock mode set-up

(Refer to the table 4.)

OCKS1

OFF

OCKS0

OFF

MCLK frequency set-up

(Refer to the table 5.)

Table 3. S1 set-up

CM1

(S1-2)

CM0

(S1-1)

MCKO

SDTO

OFF

TORX or BNC

OFF

X'tal

"0" data

Table 4. AK4112A clock mode set-up

LRCK

OCKS1

(S1-3)

OCKS0

(S1-4)

MCLK

Normal

Double

OFF

256fs

Yes

OFF

512fs

Yes

Table 5. AK4112A MCLK frequency set-up

ASAHI KASEI

[AKD4382]

'00/09

- 5 -

PORT3

uP-I/F

CSN

CCLK

CDTI

Jumpers set up

[JP1](TORX/BNC): The source of the biphase signal input to the AK4112A

TORX: PORT1(TORX176: optical link) <default>
BNC:

J1(BNC)

[JP2](GND): AGND and DGND

Open: AGND and DGND are disconnected. <default>
Short: AGND and DGND are connected. ( "DGND" jack can be open.)

[JP3](REG): VDD of the AK4382

Short: VDD is supplied from the regulator ( "4382_VDD" jack should be open). <default>
Open: VDD is supplied from "4382_VDD" jack.

[JP4](MCLK): MCLK of the AK4382

Short: MCLK is fed from the AK4112A. <default>
Open : MCLK is fed from the external circuit via PORT2(EXT).

[JP5](BICK): BICK of the AK4382

Short: BICK is fed from the AK4112A. <default>
Open : BICK is fed from the external circuit via PORT2(EXT).

[JP6](SDATA): SDTI of the AK4382

Short: SDATA is fed from the AK4112A. <default>
Open : SDATA is fed from the external circuit via PORT2(EXT).

[JP7](LRCK): LRCK of the AK4382

Short: LRCK is fed from the AK4112A. <default>
Open : LRCK is fed from the external circuit via PORT2(EXT).

The function of the toggle SW

[SW1] (PDN): Resets the AK4382 and the AK4112A. Keep "H" during normal operation.

The indication content for LED

[LE1] (ERF)

: Unlock and parity error output of the AK4112A.

[LE2] (FS96)

: 96kHz sampling detect of the AK4112A.

[LE3] (AUTO) : Non-PCM data (AC-3, MPEG etc.) detects of the AK4112A.
[LE4] (V)

: Validity detect of the AK4112A.

Serial control

The AKD4382 can be controlled via the printer port (parallel port) of
IBM-AT compatible PC. Connect PORT3(uP-I/F) with PC by 10-wire
flat cable packed with the AKD4382.

Take care of the direction of connector. There is a mark at 1pin.
The pin layout of PORT3 is as Figure 4.

Figure 4. PORT3 pin layout

Электронный компонент: AKD4382